1. Field of the Invention
The present invention relates to FinFET devices and in particular to improving the stress-enhanced performance of FinFET devices using one or more surface/channel orientations and one or more strained capping layers.
2. Description of the Related Art
Conventional field effect transistors (FETs) have a planar structure in which the surfaces of the source, drain, and channel are located substantially in the same plane. In contrast, FIG. 1 illustrates an exemplary non-planar transistor, i.e. a FinFET 100. In this embodiment, FinFET 100 includes a source 101, a drain 102, and a channel 103 that is formed along the sidewalls of a vertical, silicon “fin”. A gate oxide (not shown) and a hard mask 105 (formed from an insulating layer) isolate a gate 104 from the other transistor elements of FinFET 100.
As shown in FIG. 1, gate 104 straddles channel 103. In this configuration, gate 104 can be characterized as being two gates in planes on either side of channel 103. This gate and channel structure can effectively enhance gate control and drive current. In one embodiment shown in FIG. 2, spacers 201 can be formed on either side of gate 104 of FinFET 200. Spacers 201 can be used to protect the channel from impurities to be implanted in source 101 and drain 102 (thereby ensuring that source 101 and drain 102 are conductors, but keeping the channel a semiconductor). Both FinFETs 100 and 200 are described in further detail in U.S. Pat. No. 6,413,802. FinFETs are expected to replace the current state-of-the-art bulk CMOS transistors at the 32 nm technology node.
Stress engineering has been recently introduced to boost performance of CMOS transistors. As used herein, the term “surface” (shown generically as “(XXX)”) refers to the crystalline orientation of the wafer surface, whereas the term “channel direction” (shown generically as “<XXX>”) refers to the crystalline orientation of the current. Notably, production CMOS transistors have a single standard surface/channel direction combination, i.e. (100)/<110>. Moreover, typical stress engineering used in the industry is a simple uniaxial stress pattern.
For FinFETs, there are more surface/channel directions to choose from. Thus, stress engineering can potentially include complex 3-dimensional stress patterns rather than simple uniaxial (or biaxial stress) patterns. U.S. Patent Publication 2006/0284255 (filed by Shin, entitled “Complementary Field-Effect Transistors Having Enhanced Performance With A Single Capping Layer”, and published on Dec. 21, 2006) teaches one embodiment in which NMOS transistors are formed in silicon having a (100) surface and PMOS transistors are formed in silicon having a (110) surface. For the (100) surface, a tensile film (capping layer) induces tensile stress in the channel region of the NMOS transistors, which improves electron mobility in the stressed silicon. In contrast, for the (110) surface, the same tensile film (capping layer) induces compressive stress in the channel region of the PMOS transistors, which improves hole mobility in the stressed silicon.
In another embodiment, Shin teaches forming NMOS transistors in silicon having a (110) surface and forming PMOS transistors in silicon having a (100) surface. For the (110) surface, a compressive film (capping layer) induces tensile stress in the channel region of the NMOS transistors, which improves electron mobility in the stressed silicon. In contrast, for the (100) surface, the same tensile film (capping layer) induces compressive stress in the channel region of the PMOS transistors, which improves hole mobility in the stressed silicon.
In summary, Shin teaches that a single stressed layer of silicon nitride can be formed over the entire transistor structure (e.g. FinFET 100 or 200) to induce stress in the channel region (wherein the type of stress depends on the surface crystalline orientation of the channel). This capping layer can enhance mobile carrier mobility. Shin does not address the effect of channel direction on performance or the use of multiple stressed layers.
Therefore, a need arises for a method and a structure to improve carrier mobility in FinFETs. This method and structure can advantageously take into account the effect of channel direction as well as multiple strained capping layers.